1. Field of the Invention
The present invention relates generally to package substrates and fabrication methods thereof, and more particularly, to a package substrate with a single wiring layer and a fabrication method thereof.
2. Description of Related Art
Lead frame package substrates have long been used due to their low fabrication cost and high reliability. In particular, lead frame package substrates are cost-competitive for semiconductor chips with low I/O counts.
In some cases, package substrates for simple electronic products only need a single wiring layer.
FIGS. 1A to 1G are cross-sectional views showing a package substrate having a single wiring layer and a fabrication method thereof.
Referring to FIG. 1A, a carrier board 10 is provided, which has two opposite surfaces each having a copper layer 11 disposed thereon.
Referring to FIG. 1B, a resist layer 12 is formed on one of the copper layers 11 and a plurality of openings 120 is formed in the resist layer 12 to expose portions of the copper layer 11.
Referring to FIG. 1C, the exposed portions of the copper layer 11 are removed so as to form a wiring layer 111 on the carrier board 10.
Referring to FIG. 1D, the resist layer 12 is removed.
Referring to FIG. 1E, a plurality of through holes 100 is formed in the carrier board 10 by a laser, each penetrating to the wiring layer 111 at one end thereof.
Referring to FIG. 1F, a first insulating protection layer 13 is formed on one surface of the carrier board 10 with the wiring layer 111, and a plurality of openings 130 is formed in the first insulating protection layer 13 for exposing portions of the wiring layer 111; and a second insulating protection layer 14 is formed on the other surface of the carrier board 10 and a plurality of openings 140 is formed in the second insulating protection layer 14 to expose the through holes 100.
Referring to FIG. 1G, a surface-processing layer 15 is formed on the exposed surface of the wiring layer 111 so as for mounting of solder balls (not shown).
Since the package substrate comprises the carrier board for supporting the wiring layer, the package substrate has a thickness of about 130 μm, which is close to the thickness of a package substrate with double wiring layers, thereby adversely affecting the miniaturization of electronic products.
Therefore, it is desired to provide a package substrate and a fabrication method that overcomes the above-described drawback.